Ak-cmsis-dap clock is too slow

Support
#1

Hi,

I’m using AK-CMSIS-DAP with firmware 1.1.
I’m running openocd 0.12
I use an oscilloscope to measure the frequency of pin TCLK/SWDCLK
I run this command:
openocd -f interface/cmsis-dap.cfg -c "adapter speed 2000" -c "transport select jtag"

The measured frequency of TCLK is 299KHz instead of 2000KHz
If I use other adapter speed values, I always measure lower frequency on the bus, here is the table of measurements:

| Openocd KHz | Bus KHz |
|-------------+---------|
|         100 |      28 |
|         500 |     118 |
|        1000 |     198 |
|        2000 |     299 |
|        3000 |     251 |
|        4000 |     266 |

Are you aware of this problem?
How do we use higher frequencies?

Thanks

#2

Hello,

We are checking this. I will write an update in the following days.

#3

Hello,

I’m sorry for this taking so long. The person that masters this project is out on holidays and comes back later this week.

I can just say that I reproduced the issues you see.

#4

Hello,

The answer is that the AK-CMSIS-DAP is trying to match the requested speed but can’t make it, since it’s driving the SWJ lines by moving GPIOs (and it’s a Cortex-M0+ @ 25Mhz).

Even though, there is an ongoing effort to release a new version SW with timing improvements, but the ETA is not known at the moment.

#5

Yes, I’ve seen that your SW is based on absolue cycles count between clock changes which doesn’t take into account the processing time. You should use systick interrupt to trigger the clock change action.
Moreover, you define DELAY_SLOW_CYCLES to 3 cycles which is not possible on Cortex M0+. My estimation is 10 cycles which improves actual bus speed.